This invention relates to digital signal processing (DSP), and more particularly to architectural considerations relating to word conditioning and analysis operations for DSP processors.
In conventional DSP processor architectures, logic for performing word conditioning operations (e.g., rounding, saturation, etc.) is typically included in substructures such as arithmetic logic units (ALUs) and accumulators. As a result, the delays associated with propagating signals through word conditioning logic often appear in the critical paths of functional blocks (e.g., multiplier-accumulator (MAC) blocks) that use such substructures. If analysis operations are also required, a further delay could be introduced before the output of a given functional block may be available for use by other functional blocks or subsystems. For example, in block floating point analysis, additional instructions are usually required to perform this analysis in a separate functional block.
The above-described delays which appear in the critical paths in conventional DSP processor architectures are especially pronounced in “soft logic” implementations, such as those on programmable logic devices, wherein word conditioning operations are implemented by logic that is multiple levels deep, thereby incurring considerable propagation delay. These delays may be further compounded by inefficient arrangements for performing analysis operations.